Design Of Transient Power Quality Disturbances Detecting Algorithm IP Core Based On FPGA

With the rapid development of scientific technology and national economy, the factor that causes power quality problem unceasingly increases. So the power quality is put forward a higher requirement. Power quality can be mainly classified into stable and transient power quality. It is hard to acquire all kinds of information of the transient power quality disturbances in time by the existing detection technology of power quality, because of variety and complexity of the disturbances. Therefore the detecting and analyzing of transient power quality disturbances is an important research subject about, and it has important realistic significance.Based on the research of both home and abroad, the detecting methods of a few familiar transient power quality disturbances is analyzed and studied in this paper. And a design of transient Power quality disturbances detecting algorithm IP core based on FPGA is completed. The simulation results based on FPGA show that the designed IP core can accurately detect the voltage sags, swells, interruptions and oscillations.The singularity of signal can be showed by wavelet transform modulus maximum because of its good time-frequency localization. The paper uses DB4 wavelet transform to detect the transient power quality disturbances and the obtained algorithm can detect the voltage sags, swells, interruptions and oscillations. The simulation results in the Matlab environment show the accuracy and effectiveness of the detecting algorithm. Very-High-Speed Integrated Circuit hardware description language (VHDL) and FPGA are used to realize the above algorithm. The results show that the detecting algorithm achieves excellent detecting effect and has the advantages of recognition of many kinds of signal and high recognition accuracy.In order to eliminate high-order harmonic to reduce the influence to transient power quality detection, the paper designs a 64-step FIR filter based on FPGA to increase the detection accuracy. The design and simulation of filter model are accomplished by using Altera DSP Builder and Matlab/Simulink, respectively. The DSP Builder can convert the designed filter model directly into VHDL codes which is needed to accomplish the filter on FPGA .On the Quartus II platform, the timing simulation and FPGA Synthesis of filter are completed. Using DSP Builder, the method to design the FIR Filter by combining Matlab/Simulink and Quartus II design tools together well is simple and effective.Then 64-step FIR filter and DB4 wavelet detection algorithm module are respectively added to SOPC Builder's component in the form of user define external device to create IP cores. The designed IP cores which can be directly invoked by the users has the own Intellectual Property and good application prospect.Finally, the summarization and prospects of the research are described.