Design Of Two-order Differential Interface Circuit For ΣΔ Micro Accelerometer

ΣΔmodulations are acknowledged as the optimal means by which to implement digital accelerometers. The feedback closed-loops of micro-accelerometers, implemented by means ofΣΔmodulator, show features of large operation bandwidth, simple structure and manufacturing by CMOS process at ease. Having analyzed a variety ofΣΔmicro-accelerometers in forms of different implementations, a two order system ofΣΔmicro-accelerometers is designed, and they are further realized by SC differential interface circuits.In this paper, a two-order system is built and test by Matlab. The result demonstrates the SNR of an input signal with a frequency of 500Hz is able to reach 84.8dB. In such a system, the function of interface circuit is to transform capacitance to voltage, amplify signals, and compensate phase lag. The analysis on non-idealities of a two order delta- sigma modulator was presented. Non-ideal behavior model is established and sampling jitter, KT/C noise, switch non-linearity and electrode movement are modeled with emphasis. The effect of sampling uncertainties'standard deviation, sampling capacitor and electrode elasticity coefficient to the system are particular analyzed in this paper. Other modulator non-idealities'effect to this system are also discussed here.The circuit is divided into full bridge module, charge sense amplifier module, holding module, capacity compensator, high speed comparator and time controlling module etc. Based on these models, interface circuit is designed. Charge-voltage transformation is realized by low noise charge integrators. CDS technique is applied to decline low-frequency noise, compensate the offset of op amps, and suppress the impact of finite gain. A feed forward compensator is used for stability. Here we analysis machine-noise and electrical noise including opamp noise, wiring resistance noise and the reference voltage source noise in this system. Finally the whole system is simulated by Hspice. The simulation result by Hspice shows that with an input signal with a frequency of 500Hz and 1g acceleration, the noise density is 10μg/ Hz and the system sensitivity is 0.48 v/g. The result of simulation shows that this system realizes the required function.