Desig Of The High Efficiency-low Power DC/DC Step-up Switching Power Supply

The aim of this subject from DaLian LianShun Electronics company is to design a high-efficiency low-power DC/DC step-up Switching Power Supply. We use the principle of SG3525A for reference and adopte forward design methodology as the main approach with the aid of backward design by Bi-CMOS technology. Low power structure is considered as the first choice in the basic of split the difference of other parameters, at the same time the system can automatically come into waiting state or sleeping state when in light load by added the enable control end in each unit circuit, accordingly improving the efficiency and reducing power. And in order to improve the efficiency and reduce power more and more, we have optimized-designed and analysed the switching transistor and the external inductance and capacitors. This system adopts PWM modulation model with comparatively simple structure and current control model with rapid response, including bias, band gap reference voltage, error amplifier, comparator, oscillator, under voltage lockout protection, over current protection, slop compensation etc. Reference voltage which determine the precision of the output adopts the band gap reference voltage structure, it has favorable temperature and voltage characteristics by elaborately design and obligate trimming resistor, temperature coefficient is zero at room temperature, voltage characteristics is 10ppm between 2V to 10V, the value of reference voltage is 1.17V. Slop compensation efficiently prevents instability of the output when the duty cycle of switching transistor pulse more than 50％, resolving the problem of power's out control when in light load or no load and dealing with over current protection problem. Error amplifier in this system is designed with high gain at low frequency and low gain at high frequency, it has 3M gain band width product and 80~ phase margin by external capacitor.The simulation adopts PSPICE BSIM3v3 Model Parameters, its results shows that the design satisfy requires and with ample margin. Completing the whole layout with L-Edit followed CSMC 1.2μm silicon gate N-well Bi-CMOS technology, and then edit extract file to extract net list of the layout, verification of LVS shows no error. Under voltage lockout protection occurs when input direct voltage smaller than 2.35V; output adjustable from 2.6V to 15V; 1％conversion precision in moderate load; quiescent current 10μA; 85％conversion efficiency; 600kHz oscillator frequency and duty cycle of PWM adjust from 25％—75％.