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Research On Pulse Width Modulation Strategy For Neutral Point Clamped Multilevel Inverter

Posted on:2008-08-26Degree:MasterType:Thesis
Country:ChinaCandidate:H A WuFull Text:PDF
GTID:2132360242460765Subject:Power electronics and electric drive
Abstract/Summary:PDF Full Text Request
Recent years, multilevel inverter has been popular researched in the high-voltage and large-capacity area of electrical energy transformation due to their advantages regarding large power export, low harmonics, high power factor, etc. Especially three-level inverter is widely studied and the corresponding product is applied to industry. Aim at multilevel NPC inverter, this dissertation will stress on the related question of carrier PWM and space vector PWM (SVPWM) modulation strategy. The main contents of this paper are as follows:1. The dissertation presents a review of multilevel inverter background and actuality firstly. Then three kinds of topology structures and modulation strategies of multilevel inverter are introduced respectively, and the principle of three-level NPC inverter is stated explicitly.2. In view of the unity of carrier PWM and SVPWM, three kinds of five-level inverter carrier PWM is investigated and the equivalent synthesizing rules between these three carrier modes and SVPWM are studied. The equivalent space vector sequences are proposed for these carrier strategies. The harmonic voltage amplitude of these carrier modes is acquired by using Fourier analysis with variance of modulation index.3. Based on traditional SVPWM algorithm of three-level inverter and the reason of neutral-point voltage imbalanced is brief introduced, different vectors influence to output voltage wave is analyzed. A new SVPWM control method considered neutral-point voltage balanced is proposed and simulated based on Matlab7.0. The simulation result is obtained and reve'als the method is superior.4. Owing the switch sequence and dead-time problem will increase the THD of output voltage, a consideration of symmetrical SVPWM pattern with dead time compensation method is proposed. The design of experiment platform and control plan based on FPGA about this method is realized and then experiment is completed on three-level NPC inverter with motor load. Experimental result is given in the paper and proves the design of hardware and software is correct.Finally, the summary and expectation of multilevel inverter research is provided.
Keywords/Search Tags:Carrier PWM, SVPWM, Neutral-point Voltage Balanced, Dead-time Compensation, FPGA
PDF Full Text Request
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