Research On The Channel Multiplexer/Demultiplexer In CCSDS AOS And Its Implementation Based On FPGA

The CCSDS AOS plays a more and more important role in aerospace technology, while Channel Multiplexer/Demultiplexer and virtual channel scheduling become cores of AOS ISS data system, and be critical for AOS to transmit multi-services, high-speed data.Based on the study of CCSDS Advanced Orbiting System, this thesis makes analysis on AOS system structure, operational characteristics.Channel Multiplexer/Demultiplexer, the key part of the AOS ISS data system, is critical in transmitting multi-tasking data with different bit rates. In analyzing this system, the author employs 5 channels (including a detail-investigating camera with bit rate of 150 Mbit/s) to transmit various bit rates characterized signals, and the transmission VCDU is 4080 bits. After that, the channel Multiplexer/Demultiplexer's performance is determined, as well as the task needed by Virtual Channel Strategy.LVDS(Low Voltage Differential Signal) standard is chosen to be the data interface voltage standard between the Channel Multiplexer and the Channel Demultiplexer and to be the standard of other interfaces on account of whose advantages such as high-speed transmitting, low noise, low power consumption and high integration level in related applications.On the basis of works mentioned above, a channel Multiplexer/Demultiplexe design solution has been provided, which include the architecture of the channel Multiplexer/Demultiplexer and its modules, the realization of the insert business, the selection of data memory, the interfaces design between channel Multiplexer and Demultiplexer and other link controllers based on Handshake principle for data transmitting.The method of Virtual Channel Scheduling determines the transmitting sequence when VCDU is transmitted to physical channel, and a dynamic scheduling strategy of Polling weighted approach is offered to against the disadvantage of channel monopoly caused by polling method with priority. With the work analyzed, it's found that data's utilization of 5 physical channels can be mostly realized.System design is completed with its core, XC4VFX12 FPGA chip,Virtex-4 series. All the logic code design is written in Verilog HDL language.A testing system using Tektronix TLA5201 logic analyzer system is built for observing data stream transmitted in system. It's found that during the test, the system works well, channel Multiplexer/Demultiplexer are able to multiplex and demultiplex data consistently, the data stream transmits fluently without data lost.