The Design Of Low Power High Stability LDO Linear Regulator

With rapid development of power IC technology, high performance low cost power management chips become more and more popular. LDO linear regulator is widely used in various kinds of DC regulating voltage circuits, for the benefits of low noise, high power supply rejection ratio (PSRR), micro power loss, and simple peripheral structure etc. In order to meet the needs of power market development, combining with self features of LDO system, this thesis proposes a kind of LDO linear regulator with low power and excellent stability.Firstly, this thesis gives a brief introduction on working principles and basic indicators of LDO regulator. System structure will be deeply discussed in TRAN, DC, AC three aspects and designing key points along with various parameter trade-off relationships will be expounded subsequently. Then, optimums every sub-module and determines the final system architecture from the angle of low power design. In order to obtain the path to research on stability of LDO system, calculates loop gain and deduces zero-pole distribution by setting up AC small signal models. Nested miller compensation (NMC) and Tracking-frequency compensation will be introduced to ensure the stability of LDO topological structure which adopts two stage cascade error amplifier driving pass element directly. Discusses probable situation of nulling resistor in NMC circuits, and eliminates effect of right-half-plane zero effectively by fixing a best compensation structure. Analyzes structure and working principle of every sub-module in detail, simulation results of whole chip will be shown in the end.Circuit design is based on CSMC 0.6um CMOS process and simulation has been completed under different combinations of spice models, supply voltages and operating temperatures. The whole chip cost static current of 1.79uA, bandwidth is almost constant and the system keep excellent stability under whole output current range.