Design Of The Core Blocks In Low-Dropout Voltage Regulator

Demands for power management chips is getting higher and higher for the rapid development of mobile phones, laptops and other portable devices in recent years.Power management chips are developing toward miniaturization, low power consumption and energy saving direction.LDO is a low dropout voltage linear regulator. It has been among the best in the power management chip market,for its advantages, such as small quiescent current, low noise, high resistance to electromagnetic interference and fast transient response when compared to other regulators. LDO has been widely used in medical, computer, infrastructure and many other fields. Currently, LDO is developing towards low power, low quiescent current, fast transient response, large output current, and many other directions among which Large output current is an important one. but the large output current can cause the stability problem of the LDO loop. Therefore, the design of LDO with a high current, high stability is of very real significance.The proposed LDO is composed of band-gap voltage reference,error amplifier,PMOS regulator and feedback resistors.The feedback circuit consists of the error amplifier,PMOS regulator and feedback resistors.The core of the band-gap voltage reference is a two folded cascade operational voltage amplifier; the realization of the first order temperature compensation is based on the negative temperature coefficient effect VBE and the positive temperature coefficient effects of and the second-order temperature compensation has been realized through the diode Reverse saturation current with positive temperature coefficient. The nested Miller compensation method is used to insure the stability of the LDO when load current changes. In addition, a temperature protection circuit,which translates temperature signal to voltage signal making using of the negative temperature coefficient of VBE,has been designed to provide good over-temperature protection for the LDO.A LDO with a maximum output current of 1A is proposed in this paper. This LDO can work normally when supply voltage ranges from 3V to 5V and the output voltage can reach 2.5V. The circuit has been simulated with Hspice in TSMC 0.35 um standard CMOS process and the simulation results show:the dropout voltage is 180mV when the output current is 1A and line regulation is 0.47m V/V;Variation of the linear transient response is 40mV when the load current is 500mA and supply voltage changes from 3V to 5V;the load regulation is 0.4%mV/A and Variation of the load transient response is 25mV when load current changes from 0A to 1 A.