Research Of A Low-Drop-Out (LDO) Linear Regulator

Owing to the popularity of portable electronic products, the consumption of supply IC is enormously increasing, which results in the enlarged supply IC market. Low-drop-out linear regulator has a large anticipated market for its many advantages such as high integration, high performance price ratio, simple peripheral equipment and high precise output voltage. Consequently, there is great significant to carry out this project.This research which is funded by the project of the National Natural Science Foundation of China (NSFC) realized a low-drop-out linear regulator. Its output voltage is constant 3.3V while the input voltage range is 3.5V to 6.5V during the operational temperature range of -40℃to 85℃. The results of simulation indicate that when the load current is 150mA the least dropout voltage is no more than 200mV with an output voltage precision of±1%.The necessary cuicuits of LDO are designed, including a bias current source, a voltage reference, an error amplifier and its control circuit, sampling resistors and a pass element. All these circuits form a negative feedback, which produces a steady output voltage. A thermal protection circuit and a current limit circuit are added to protect the chip to work permanently. The former module consists of a hysteresis comparator which avoids the dithering around the temperature threshold and reduces the variation of temperature threshold with different supply voltages. The latter module which employs a fold-back structure current limit circuit reduces the power consumption when the load resistance is too low. Moreover, this chip possesses an enable pin EN and a POK pin indicating the state of output voltage for the next level circuit out of the chip. Considering the above structure, this chip provides high efficiency and consumes little power. It can perform steadily under different input voltages and load currents, only needing simple peripheral equipment of two capacitors with 1μF value.The schematic is designed through 0.5μm CMOS process on IC design and simulation software Cadence and Hspice. Then the layout of this chip, which is designed and validated on Virtuoso integrated in Cadence, is fabricated through the multi-project wafer service in Wuxi Shanghua Semiconductor Corporation. Sequentially the samples of the IC are tested and the results of the test are analyzed. The test of the chip proves that this regulator can provide a steady output voltage and the functions of enable pin and POK pin are also realized successfully under different input votages and load currents. The precision of the output voltage can achieve to±1% satisfying the requirement of the guide line, except the condition that the input voltage is over 5V and the load current is over 50mA. In the end some optimization methods are proposed.