Research And Implementation On SCI/RT Node Based On FPGA

The State 863 Project "flight control computer system developed FC Communication Card" is the task of research and design consistent with the FC CPCI bus standard communication cards,The issue is the further extension of this project,on the basis of its design to meet the SCI/RT agreement interface model,and in each SCI/RT data communications nodes into the priority of judgement,to meet the real-time data transmission requirements.As this paper background,SCI/RT nodes is Researched and Implementated on the FPGA-based.At first,the paper outlines SCI protocol and SCI/RT protocol,and analyses the similarities and differences between the two protocols.Second,Digital hardware development is introduced for a design basis.Third,it introduces SCI/RT interface and the overall detailed design and finally goes along hardware logic simulation test.SCI/RT node model includes send and receive memory,FIFO bypass,address decoding,state management registers,multiplexer,Aurora modules and high-speed serial communication interface,such as RAM memorys on FPGA block achieve send and receive;the use of synchronous FIFO design achieve bypass FIFO;the FPGA embedded RocketIO transceiver achieve high-speed serial console between the high-speed serial communication nodes,and use Aurora IP realized Aurora link layer protocol;address decoding and multiplexing respectively is used to realized the control logic;finally,the adoption of OPB-PCI bridge realizes CPCI interface logic.The issue use SOPC scheme to achieve the programmed FPGA logic design. Verilog hardware description language is used to achieve bypass FIFO;VHDL hardware description language is used to achieve Aurora link layer module.Xilinx ISE is respectively used in the realization of bypass FIFO module functions and the time sequence simulation of Aurora model;Xilinx EDK is finally used to achieve the overall design,and download the development board to use ChipScope Pro-Logic Analyzer to verify the design result,by comparing the simulation results,it is accorded with pre-meet expectations,which proves the correctness of the hardware logic design and feasibility.Finally,the paper summarizes the work of research,point out the deficiencies in this development,and put forth suggestions for further improvement programmes.