Design And Implementation Of JPEG Coding System Using VHDL Language

This thesis consisted of designing and implementing a JPEG coding system by VHDL language. JPEG is a commonly used digital image compression algorithm officially known as ISO Standard 10918-1. JPEG coding allows digital images to be stored in a compressed form that achieves anywhere from 12:1 to 100:1 depending on the acceptable loss in image quality of the compression.This JPEG coding system is primarily intended for use in consumer electronics devices such as digital cameras. This use requires the design to have a number of features including low price, low power, compact design, and high speed. To meet these requirements the system was designed as a custom digital logic component described in the standard hardware description language VHDL (VHSIC Hardware Description Language). This type of design is a high-level description of the system that is then translated into a digital circuit by EDA soft. Now,the programmable chip's clock becomes faster and faster ,the capability of programmable chip is improved very fast also,so more complex function can be implemented in one chip.This design can implement as JPEG coding chip in FPGA, it can be used as IP core to other designs.A number of challenges needed to be met to design and implement a JPEG coding in hardware rather than in software running on a microprocessor. JPEG coding normally requires many floating-point multiplication calculations. Since the multiplication calculation cost more chip area than add calculation and the floationg-point calculations are not efficiently implemented in custom hardware they were replaced by scaled fixed-point approximations. Also the JPEG coding algorithm requires a substantial amount of memory. To reduce the number of multiplyer the quantization table is especially designed to avoid divide calculation. In order to read data and simulation efFectively,FIFO and bit-to-byte function is designed also.This JPEG coding system is designed and simulated by QuantursII software which is the FPGA design tool of ALTERA company . Hole design need nearly 12600 LCs of Cyclone device.