Implement Of E1/CT-BUS Frame Justification With FPGA

[Abstract]Along with the science progress, the computer network, the communication network and the consume network are coming up together. 3 C in 1 is the tend of the network development, which is proven by CTI( Computer Telephony Integration). As well known, the communication field is composed of switching and transportation. Information is transported through a synchronized path, so the pulse justification and the frame justification are the mostly adopted methods. In the trunk line, the pulse justification technology is the best way to provide a synchronized path, this method can only trace the wander, instead of erasing the wander, some time it even bring additional wander into the path. In the digital switching network, the voice path is the unit be used for channel-crossing .The trunk data stream from different directions are splitted into some voice paths to deliver to the switcher. The voice paths are multiplexed into a new trunk stream be transmitted to others directions, while no any variant wander is allowed in these paths. So erasing wanders between the paths is the key to implement switching and multiplex. At the time, the pulse justification technology is not suitable for the case, the frame justification technology takes its place. The frame justificater is set between the trunk line and the digital switcher, in other word, The frame justificaters are set at the entrances to the switching network. There are wanders among nodes of trunk line, where must be the frame justificaters. The local clock replaces the clock from incoming stream, so the frame justificater implements bit-synchronization; the slip substitutes the jitter and the wander, and the data stream from others directions are synchronized to the local timing by frame delay.This article provides the FPGA design idea of E1/ CT-BUS frame justification , including the complete E1 framer ,and justificater, and E1/ CT-BUS multiplexer, and clock recovery, and clock smoother. So additional modification done, this design can be used in the Sc-bus and H-MVIP, and especially used CTI .If working with MCU, the chip can impletments high scale exchanger among timer slots , it is frequently used in voice application.The scheme of chip FPGA design is completed by a top-down design flow in which Verilog HDL description is used for its text file design, synthesis, simulation, place and layout, etc, are included.