The Research Of One RISC-DSP-based Dual Core System-on-Chip

With the developing of IC (integrated circuit) technology, SoC (System-on-Chip) have become one of the hot spot of IC design by having many advantages including small volume, high working speed, low cost and IP (Intellective Property) core reusable. Some IC design companies have manufactured self-owned IP SoC chips one by one. In SoC design, processor design takes the main proportion. The SoC technology of processor has wide prospect because it can apparently enhance the working efficiency of the whole system and offer good cost-effective.Facing industry control and low-edge signal process, the thesis mainly studies the design method of dual core SoC of RISC microprocessor and DSP. AS main processor, the microprocessor takes the simplified architecture of ARM processor. Meanwhile, DSP takes the simplified architecture of C54-based. Host Port Interface of DSP implements interprocessor communication. Verification and synthesis of the system is through the action description of it by HDL (hardware description language) language. The thesis is organized as follows:Chapter 1 briefly introduced background of SoC technology and developing condition of SoC processor. Then introduced the main work of the thesis in sum.Chapter 2 discussed some main architecture of SoC processors and analyzed their advantages and disadvantages. The thesis focused on a solution of RISC-DSP-based dual core SoC, introduced the collective architecture of all main parts of the solution, and particularly analyzed the way of interprocessor communication.Chapter 3 discussed the design method of SoC, testified the superiority of verification and synthesis of the system by using HDL, and introduced the method of the thesis in the verification of SoC solution.The last two chapters is the kernel part of the thesis. It mainly introduced the verification and synthesis of the master processor and DSP. Chapter 4 analyzed the architecture of the master processor and did the verification and synthesis work to its sub module. Chapter 5 analyzed the architecture of DSP and did the verification and synthesis...