Design Of The High-Speed Parallel Frame Alignment In VSR System

With the fast development of Internet and telecommunications, the extensive application of multimedia communication of audio and video , the bandwidth of networks was required bigger and bigger, the optic communication has already become the foundation of the information superhighway, synchronous digital hierarchy (SDH) already became the world's high speed communication standard.At present, a large amount of optic network equipment is put in the same room of the service provider of the telecommunications. In order to reduce the cost of interconnecting between high speed optical equipments, optical internetworking forum (OIF) had made a serial of implementation agreements of optic interlink within very short distance, namely VSR interface agreements. Its key intention is to replace high speed serial parallel optic link with low-speed parallel optic link for lower costs.VSR is a kind of physics layers transmitting technology. At present, OIF had put forward VSR interface implementation agreements of 10Gbit/s and 40Gbit/s.VSR4-1 interface, which are studied in this article, is one of the 10Gbit/s STM-64/OC-192 VSR4 interface agreements. STM-64/OC-192 (10Gbit/s) frames are matched into parallel low-speed fibers, with 12 pairs of 850 nm multimode fibers of 1.25Gbit/s to complete full-duplex transmission. Converter integrated circuit of VSR4-1 maps STM-64/OC-192 frame into parallel optical interfaces, adding corresponding checking and correcting process.The frame synchronism circuit is the most important part of the digital transmission system.The VSR frame synchronism circuit is the most important part of the VSR system. The data of STM-64/OC-192 are striped and allied, coded, inserted the error correcting code and the frame delimiter, then transmitted through the 12 fibers, forming data stream of a new frame structure. At the receive direction, the VSR frame synchronism circuit re-allied the frame structure and make sure that the data of receive direction are synchronized with the transmit direction. Frame can be synchronized by two methods. Adopt the set adjusting method after the comparing and analyzing. On the base of the characters of STM-64/OC-192 data through the 12 VSR data channels, refer to the SDH frame synchronizing performance requirement of G.783 recommendation, choose the corresponding transmit structure and parameters to meet the SDH performance requirements.In order to raise the stability of the system, the parallel frame synchronism circuit is choosed. Following the up-down design technique, we implement the 12 channels frame synchronism circuit with Verilog HDL. The structures and simulate results of the circuits are presented in this paper. Along with the frame synchronism circuit, the bit error test system is designed in this paper.Adopting the field programmable gate array (FPGA) to implement the frame synchronism system, the VSR frame synchronism circuit is tested in the actual system as the most important module of the VSR system. It is proved that the frame synchronism system is practical and stable. The test results are presented in the paper.