Research And Implementation Of Address Computation Of A Microprocessor

X microprocessor is a high performance one, which has a powerful memory management unit. It adopts a variety of memory management techniques to map a logical address to a physical one. These techniques include features such as segmentation and paging, which allow memory to be managed efficiently and reliably. The address generation unit (AGU) is a key component of the memory management unit and is used to compute the Effective Address and Linear Address of the location being addressed in memory.The paper investigates the mechanism of AGU and describes the architecture of unit circuits. A settlement is supplied to work out downward compatibility when performing arithmetic operations on a plurality of digital inputs to produce an Effective Address and a Linear Address in parallel. Additional, those problems just as comparison between segment limit with EA and multiplication between Scale and Index address are also solved.Address computation is a performance-critical operation that requires a high-performance adder. In order to enhance the efficiency of the CPU pipeline, two kinds of 32-bits adders are introdued in the paper. One adder is an improved CLA and the other is based on Kogge&Stone algorithm.The logic level of the improved CLA circuit is only 3 stages. The conditions of carry propagation are weakened and operation delay is reduced. Through SPICE simulation, the speed of the adder is about 320 ps. The other one need 6 stages circuit to realize the 32-bits adder, which is 141ps slower than the first one. But the power and area are more suitable for the design of the X-CPU, consequcely the second one is chosen.