IP Low-power Design And Verification For DMA Controller Controller Based On AMBA

This thesis is based on a general-control SoC(system on a chip) program, and do low power design and verification for the DMA controller IP. AMBA architecture is adopted in the system, there are SD controller, USB device controller, EBI and other master devices, which access the on-chip SRAM and occupy CPU and bus resources too much. The DMA controller designed in this thesis provide DMA access mode to reduce over-occupancy of CPU and bus, so system efficiency is promoted. Comparing to the general DMA controller, there are eight DMA channels in the IP, each of channel has priority configuration register and control register, the judgment of priority between channels is charged by priority configuration register, the burst transmission length and the roll back length is configured by the control register. DMA mode can be changed by writing in these registers, and also according to the writing of registers, the DMAC has the following characteristics: two sets of AHB interfaces, eight DMA channels, configurable priority arbitration, the burst of DMA transfer in each channel can be configured to 1-16, the roll-back length in each channel can be configured to 0-3.Power consuming is considering strictly on low-power design. Several low-power designs are analyzed and compared. According to circuit structure of this IP, gated clock management and blocking memory are applied in the IP, the results are satisfied through software simulation, power consumption reduced to 21.8%. The design has passed functional simulation, timing simulation and system simulation, the paper gives simulation waveform about key function points.A new design of DMA controller is described in the paper, the whole flow of circuit design is illustrated from low power technologies, system verification and power estimation.