Research On Key Technology Of Multithreading Processor In Multi-Processor SoC

Recently the bandwidth of the Internet is increasing continuously, this does not only mean that there are many kinds of enormous data flow to deal with, but also induces lots of new services coming up, such as conferences through network, live videos'play, virtual private network and so on. These services have stepped into people's lives. So this makes a high expectation on network processors'performances (10⁹¹0¹²bps), which work at the key point of the network. Network processors are needed to have strong enough capability of data transmission and programming flexibility to be adjusted to various network services.The data transmitting processor mentioned in this paper, as a critical part of network processor, mainly takes in charge of IP packets'transmitting. The author's research focuses on the four mechanisms of the data transmitting processor within the XDNP(XiDian Network Processor) network processor, and the simulation results of these mechanisms are given in this paper. First of all, this paper makes a comprehensive research on the 5-stage pipeline structure of data transmitting processor in XDNP. Forwarding is adopted to deal with the data reference problem; the branch prediction and defer slots are used to deal with the control reference; and relative addressing and absolute addressing are implemented to achieve the access to register of particular thread of data transmitting processor and the exchange of information among different threads. Furthermore, the data transmitting processor, described in this paper, has a multithread mechanism (four independent threads for each data transmitting processor) in hardware. This is accomplished through a series of exclusive registers for each thread to protect data, which can save the delayed clock cycles during the switching among threads. And how the thread switch is completed is explained in detail in this paper, which includes signal wake-up mechanism and non-snatched BMT (Blocked Multithreading) mechanism. At last, a comparatively reliable pause mechanism is offered in this paper. The author use a state machine to count the reference instructions in decoder stage, which can make sure to count the reference instruction in time to avoid mistake.