Simulation Design And Implementation Based On MIPS Processor

With the rapid development of IC design and technology,the design and production of large-scale SOC chips has become popular,the core technology of SOC is processor technology.Designers in order to maximize the guarantee of late development of the processor,the various functions and performance indicators consistent with the previous goal,it is an indispensable and important tool to develop a software simulator with faster running speed,higher simulation accuracy,and flexible modification,to achieve the validation of the processor architecture and reduce the development cycle of the processor.In this thesis,we use Eclipse integrated development environment and C/C++ language to realize the development of simulator based on low power MIPS processor.The main work and research contents of the simulator are as follows:(1)Simulator kernel implementation.The simulator implements the functional simulation of all instructions of the MIPS processor,it includes arithmetic and logical operations,load/store,jump and branch instructions,etc.It simulates registers and memory by defining special data structures.Simulator uses a five-stage Pipeline technology to split a single instruction into fetch,decode,dispatch,execute,and write back,the Pipeline takes various stages of the reverse execution Pipeline during the execution of simulator,the instructions of simulator implement parallel execution is exactly the same as that of processor instruction execution,it improves instruction execution efficiency.(2)The optimization of simulator Pipeline.First of all,in order to avoid the fetching instruction of the fetching stage of the Pipeline,it repeats the decoding in the next stage.The Pipeline joins the buffer queue to cache the instruction information of the decoding stage.Through the ISODATA algorithm to classify the instructions in the buffer queue to speed up the current instruction in the buffer queue recognition speed.If the instruction exists,the instruction skips over the time of the time-consuming decoding stage,otherwise the instruction is decoded,and then the other stages of the Pipeline are continued to accelerate the speed of the Pipeline.Secondly,The decoding phase of simulator is designed to reduce the unnecessary bit decoded operation of 32 bit instruction.It uses FSM(Finite State Machine)algorithm to implement the decode of instructions.The optimization of the state machine algorithm is put forward by adding the jump-out state into the state set.When FSM algorithm decodes the instruction bit,if the algorithm decodes instruction to get jump-out state,which indicates that the current instruction is not matched with the function simulation function.The algorithm exits the state transfer process.The state machine continues to iterate through the next instruction function simulation function.If the current state is accepted state,thematch is successful.The current instruction function is executed in the Pipeline execution stage.Through the above algorithm optimization of the Pipeline,the simulator increases the speed of Pipeline.(3)Simulator tests.After the above-mentioned various optimized simulators,it runs mainstream digital signal processing algorithms to test its performance.The test confirms that its function is correct,it analyzes that the performance of the optimized simulator is increased by about 15%,its accuracy error is less than 10%,it provides good reference for processor performance evaluation and functional verification.