Research On Low Power Scan-Based Testing Method

With the development of semiconductor technology, the increasing complexity of integrated circuits has brought a huge challenge to the integrated circuit testing, the increasing test data volume, test power and test application time has become the focus of our research. All of these factors will increase the cost of test, in this paper; we focused on test data compression and low power consumption method during test.In order to improve the circuit testability, scan-based DFT designs has been proposed. As all knew, when the scan-based DFT design was used for test, the power consumption during testing is often much higher than the normal mode, the power consumption is so high that will lead to A series of problems, such as the degradation of the chip function, reducing the lifetime of a chip, or even severely destroy the chip, etc.. The selected testing strategy may also lead to the fault-free chips failing the test, resulting in yield loss, therefore, testing strategy for Low-power research, has very important significance.As the importance of low-power test, there are already many ways to solve this problem, according to the need to modify the physical circuit or not, all these methods could be classified into two categories, based on the test set and circuit-based technology, while this paper, an improved scan design based method was on the scanning method.This paper first presents a test data compression method, then first analysis the character of the Linear-Feedback-Shift-Register (LFSR), and tries to reduce the deterministic bits of the test pattern, in order to reduce the length of encoding LFSR. Then a low-power scan design-based scheme was presents, first recorder the scan cell in accordance with the requirements, and then reconstructs the scan chains. To form a new low-power scanning structure, and then generate the test cube based on this structure, the generated test set can reduce average shift power consumption without cutting the fault coverage. To reduce test application time, the proposed structure based on multiple scan chains. Take the hybrid test pattern generation method, first the pseudo-random test generation, and then test generation restricted based on the structure that we proposed. When dividing the scan chains we do not use time-activated to shut part of the scan chain, so the test time will not increase, but due to the need for rearrangement of the scan cell, there will be some cabling costs.