Design And Implementation In FPGA Of Digital Predistortion Technology In IMT-A RF Transceiver System

Power amplifiers are essential components in wireless communication systems and are inherently nonlinear. The nonlinear generates spectral regrowth, which leads to adjacent channel interference. It also causes in-band distortion, which increases the bit error rate (BER). With the development of modern communication system and new broadband digital transmission techniques (such as OFDM) and high spectrum efficiency modulation techniques (such as QPSK and M-QAM) are extensive used, modern wireless communication system requests high linearity of power amplifiers. Furthermore, power amplifier also need give attention to high efficiency in wireless communication system, the linearization technique for PAs is necessary. Digital predistortion (DPD) technology as one of the most effective power amplifier linearization technology has been paid much attention to by people. In recent years, DPD technology characterized for its high performance, easy realization, low cost, has become the mainstream of power amplifier linearization solutions.This thesis focuses on the research of the digital baseband predistortion technique in IMT-Advanced RF transceiver system. It introduces the design and implementation in FPGA of digital predistortion(DPD) technology in IMT-Advanced RF transceiver system.Following three aspects are originally innovative discoveries:1. This thesis proposes a novel time delay estimation method because the loop delay estimation must be taken in consideration to ensure the correct demodulation. This method can be applied in the condition that input and output signal of PA with different sample rate. Compared with the previous methods, the computational complexity with this novel method is much lower.2. This paper builds the amplifier predistortion algorithm test system for the actual performance test and verify for digital predistortion algorithm such as ACPR, amplifiers efficiency improvement. This system provides effective guidance for the algorithm development and hardware implementation.3. In this paper, the DPD hardware solution which includes both whole DPD algorithm simulation and FPGA design is discussed in detail. We finally represent an optimized design scheme and accomplish the FPGA implementation of the DPD algorithm. The answer of the performance test can prove that this system can meet the requirements.