Multi-Standard Macroblock Prediction VLSI Design For Reconfigurable Multimedia SoC

Reconfigurable computing technique has been widely adopted for multimedia processing due to the increasing number of media formats and various standards. The reconfigurable computing arrays, facilitating the flexibility with high performance for the regular and computation-intensive algorithms in media processing, bring out a new design paradigm with a good balance between the programmability of GPP and high performance of ASIC. However, the efficiency of the irregular and control-intensive algorithms becomes the performance bottleneck of reconfigurable multimedia systems.In this thesis, an effective multi-standard macroblock prediction VLSI architecture for reconfigurable multimedia system is proposed. This architecture can achieve effective hardware reuse by supporting both H.264 high profile @ L41 and AVS jizhun profile @ L60 standards. Based on the 4x4 block level pipeline structure, the control-intensive algorithms intra mode prediction, motion vector prediction and boundary strength calculation are implemented in this architecture. An effective approach for updating neighboring blocks is presented in this thesis. It reduces the number of neighboring block registers by 64%. Furthermore, the thesis proposes a technique for pre-fetching reference blocks in direct mode prediction. The simulation results show that at least 50% latency reduction can be achieved for accessing off-chip memory.The implementation results indicate that the maximum work frequency is up to 312 MHz with TSMC 65nm CMOS technology. The proposed design costs at most 351 and 189 clock cycles to perform macroblock prediction and boundary strength calculation for each H.264 and AVS macroblock, respectively. It can meet the real-time decoding requirements for 1920x1088@30fps high definition video streams at 86 MHz frequency. Compared to other similar designs, the proposed design has obvious advantages in area and decoding performance.