Performance Study Of CMOL Circuits

With the development of Integrated Circuit, especially the application of CMOS technique, the IC feature size continues to decrease. The microprocessor with IC feature size scaling down to 32nm has come out in Intel in 2009. At the present rate of IC circuits, devices with 10nm minimum feature should become commercially available within 15 years. It means that the famous Moore-law will end if no new circuit's structure has found. Hence the research for new structure is looming ahead.With the study of nanotechnology, K.K.Likharev and D.B.Strukov proposed the structure named CMOL(Cmos/nanowire/MOLecular hybrid), which combines the advantages of CMOS technique and nanotechnology. Researchers pay great attention to this circuit's structure, and consider it will be the most promising structure. The study of CMOL technique is very limited and concentrated on the CMOL architecture, defect-tolerant model and the application of CMOL circuits. This work focuses on the performance estimation of CMOL circuits. The main contents of the thesis consist of four parts shown as follows:1.The structre of CMOL circuits is a novel one, which is implemented only by NOR logic. Hence the logical function should be converted to NOR logic based type in order to used CMOL architecture.2. The speed of IC is determined by the delay of critical path. An algorithm for finding critical paths based on branch-and-bound is proposed. The algorithm is implemented in C and tested under standard benchmarks. The proposed algorithm needs less memory and less time than those published algorithms3. The delay of CMOL circuits consits of the delay of CMOS cells located at the bottom of the architecture and the delay of two layers nanowires. This paper studies in the delay of interconnection nanowires in CMOL circuits and analyses three typical CMOL logic circuits. The proposed model is based on Elmore delay model and has tested on the ISCAS89 benchmark circuits. It provides a way of the delay estimation of CMOL circuits.