VLSI Design Of Two-Dimensional Discrete Wavelet Transform For JPEG2000

With the advent of multimedia application, the emerging still image compression —JPEG2000—had be defined as a standard in November, 2000. It has adopted "Lifting-based discrete wavelet transform (DWT)" as their transform coder, which makes Lifting-based DWT a research point.The lifting scheme has many sound characteristics. It doesn't refer to the Fourier Transform and avoids the unusable calculations in traditional wavelet transform, which leads to a lower computational complexity; the lifting scheme can be done in-place that decreases the number of memory; the hardware architecture of the forward transform is the same as that of the inverse transform, because of the reversibility of the transform; all operations within lifting scheme can be done entirely parallel. All these characteristics make the VLSI implementation of Lifting-based DWT a new research point. It is a challenge to design VLSI architecture for wavelet implementation with real-time, low area and power consumption.According to the requirement of hardware design, the study of the best hardware bit-width that satisfies the minimum JPEG2000's lossy for codec is given through the MATLAB analysis tool. In this thesis, the bit-width of the datapath, filter coefficient and input/output data is determined as 20bits, 14bits and 16bits respectively. And also a discussion for the boundary extension algorithm is given. Then, a novel method to schedule the operations involved in the VLSI architecture design for lifting-based 2-D DWT is presented. By means of processing a few datum with row filter operations that are paralleling with column filter operations, the on-chip memory capacity is progressively reduced. A VLSI architecture of 2-D lifting-based DWT that is suitable for both 5/3 integer wavelet and 9/7 float wavelet is given. It adopts pipelined method that speeds up the transforms and improves the hardware utilization. Finally, the architecture is described by Verilog HDL in register transfer level (RTL), and is simulated to verify the functional correction. The simulation indicates that this design using 9/7 filter with 3 level decompositions is able to perform compression of 1280xl024x8bit grayscale images with the speed of 21 frames per second (fps) at 50MHz system clock rate.