Vlsi Implementation Of Jpeg2000 Algorithm And System Integration

With the development of multimedia technology and Internet, the information becomes more and more, and the limited storage and bandwidth is becoming the bottleneck. So it is necessary for the effective processing and compression of information. JPEG2000 is the newest image compression standard proposed by ISO, which has the advantage of the good compression efficiency and the scalability of image quality and resolution. JPEG2000 is very suitable for the transmission of network, so it will have a bright future.Based on the detailed research about the core coding algorithms of JPEG2000, a low-memory and full-integrated VLSI architecture of JPEG2000 Codec is proposed in this thesis. Firstly, a software implementation of JPEG2000 by MATLAB is utilized for the simulation of hardware implementation. The proposed architecture has been implemented in Verilog. As for the VLSI implementation of discrete wavelet transform (DWT), the row-column based method is adopted for the 2-D DWT and a re-useable architecture for the forward and inverse DWT is proposed in this thesis. As for the hardware implementation of bit plane coding, a particular architecture of middle buffer, the method 'sample skipping' and 'pass skipping' are adopted to reduce the operation times of the memory reading, writing and operation. As for the VLSI implementation of binary arithmetic coder, a pipelined architecture based on the paralleling operation between renormalization and I-table and Q-table's reading and writing is adopted. As for the VLSI implementation of packetization and de-packetization, quantization is adopted as a rate control method to integrate the Tier-2 engine of EBCOT. At last, the hardware system of JPEG2000 is verified by FPGA VirtexE 1000e of Xilinx Corp., and the proposed architecture as a part of digital still camera has been manufactured in the standard digital CMOS 0.25 um technology of TSMC and the 0.18um technology of SMIC. The function of encoding and decoding are proven right. And the performance of the chip can meet the requirements such as digital camera.The architecture design of digital camera system is another focus of this thesis. The...