The Design And Application Of A Reusable Block Cipher Coprocessor

A block cipher coprocessor was designed and FPGA implemented. The design goal is that the coprocessor should be reusable in several kinds of application environment and the block cipher algorithm module of the coprocessor should be flexibly substituted. Three characters including hierarchical control architecture, Start-Done control protocol and RAM-like external interface were assigned to the coprocessor to achieve the design goal. It was proved that the 3DES algorithm module of the coprocessor can be substituted to AES-128 algorithm module with little modification to the coprocessor, and the same with substituting AES-128 algorithm module to 3DES algorithm module.The block cipher coprocessor has been applied in a PCI-FPGA cipher card designed by the Information Security Technology Laboratory of Guangzhou University. The application of the coprocessor in the PCI9054 local bus system residing in the cipher card was described. In order to enable cooperation the coprocessor and the main processor (Intel Pentium 4) in the progress of encrypting/decrypting the file data under Windows 2000/XP the software/hardware co-design is necessary, which is also described in the paper.Moreover, the block cipher coprocessor has also been basically applied in LEON2, which is a system-on-a-chip equipped with a 32-bit RISC processor implementing the SPARC V8 instruction architecture. With the RAM-like external interface, the coprocessor can be easily interfaced to the AHB on-chip bus of LEON2.The basic way to control the coprocessor with the SPARC V8 instructions is described at the end of the paper.The application of the block cipher coprocessor in both PCI9054 local bus system and AHB bus system with no modification well proved the reusability of the coprocessor design.