Design Of Implanted Central Nerve Recovery System And Its Stimulation Circuits

The damage of Central Nervous System, especially the injured of spines, is very popular. With the quick development in the fields of Micro-electronics as well as Neural-biology it is possible to regenerate the function of dead or damaged nerve bundles by implanting SOC (System On Chip) or integrated circuits chips, that is, Implanted Central Nerve Function Regeneration System (ICNFRS). Therefore, it is meaningful to design such systems and circuits.The ICNFRS are composed of micro-electrodes, Signal Detecting Circuits (SDC), Signal Processing Circuits (SPC) and Functional Electrical Stimulating (FES) circuits. The electrodes are the interfaces between the nerve and the system; the signals detected from the upper nerve are processed and analyzed by the internal circuits and generate the large stimulating signals which are applied at the lower part of the never. In addition, this signal transmission is in bio-direction.FES circuit is one of the most important parts in the system, and is the main subject we are focusing on in this paper. According the characteristic of the nerve stimulation, a stimulating system including data source, Core Stimulating Circuits (CSC), micro-electrodes and power supply module are presented especially the realization of CSC. Two topology, differential-phase and shifting-phase are discussed and the interface network for Cuff and Shaft Electrodes are designed respectively.With the help of the multi-channel CSC, SD mouse and rabbits'spinal cord and sciatic nerve were stimulated respectively and successfully, the stimulating threshold and the different response according to the different stimulation were gathered; the function recovery of the cut spinal cord of SD mouse was realized when co-operated with the SDC and SPC; the character of the damaged sciatic nerve was observed. The experiments results on animals showed that this FES circuits meet the requirement of ICNFRS.In addition, the FES circuits are realized with a process of 0.6μm CMOS, whose feature containing rail to rail input and output, Under the 5V supply,this circuit consumed less than 10mW, with a 90Ωoutput resistor and an area of 0.5mm2.