Low Power Design For Embedded DSP

The reasons of power dissipation on chips are studied on four levels, system level, RTL level, gate level and circuit level. The power dissipation on chips can be decreased efficiently by reducing VDD, but this method will reduce the performance of system, bus encoding techniques decrease switching frequency efficiently, and decrease the power dissipation.In the third section of this paper is the design of 16-bit fixed point low power DSP IP core with 16*16MAC and four stage pipeline is accomplished. The major building blocks of the IP core include the pipeline block(Pipe-Line), the program address generator block(PAG), the data address generator block(DAG), the central arithmetic- logic unit(CALU), the parallel logic unit(PLU) and memory controllers. The DSP has a four-stage instruction pipeline, the instruction fetch, decode, operand fetch, and execution operands are independent. The communication buses dedicated to providing the means for data transfer between the CPU and the memory. These buses tend to support heavy traffic and the energy dissipation per memory bus access is quite high, which in turn limits the power efficiency of the overall system. The emphasis of this paper is on encoding techniques for the memory address bus that minimize the switched capacitance of the bus.In this paper we study bus encoding techniques and apply low power design techniques to DSP. T0-C encoding technique is improved, more power dissipation is decreased. Several encoders and decoders are accomplished, which decreased switching activity on the bus and power dissipation. The power of PContrl block is decreased by 73.2% and the power of DContrl is decreased by 45.88%.