The Study Of Radar Signal Preprocessor Algorithm Based On FPGA

In the VTS (Vessel Traffic Services), the capability of radar signal processor has become a main factor which limits the capability and reliability of target-extracting and target-tracking of radar. With the construction of regional VTS, it is required that the radar signal should be transmitted with the highest quality and lowest cost, and the key technology to meet the requirement, which lies in the compression of radar information, is affected due to the existence of radar signal preprocessor.For the above reasons, a study on more efficient preprocessor of radar signal in VTS is very valuable and practicable. This dissertation is based on the works of former researchers. We are concerned with the principles, approaches, and performance properties studied and designed the radar signal preprocessor.The whole design is included radar signal collection, clutter processing, and the signal transmission with DSP. In hardware design, the radar signal collection, CFAR processor and signal detector are completed in FPGA. This has come true in transplanting large amount of the algorithm requiring that the chip is completed from DSP previously to FPGA, greatly, has lightened DSP chip actuating pressure , has also has diminished systematic volume.In the algorithm study, clutter suppression and target detecting are discussed. We have studied now available radar clutter suppression and signal detect algorithm, and chose the most suitable one to complete in FPGA.The applied method in the design presents theory analysis, simulation result and final result. By the design and experiment, the processor can effectively work on the collection and transmission of radar signal. The algorithm we choose can effectively suppress the pinnacle composition of the radar clutter without the loss of decreasing the resolution of target, and significantly improve the SNR.