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The Application Research Of FPGA/SOPC Technology In Digital Communication

Posted on:2007-05-24Degree:MasterType:Thesis
Country:ChinaCandidate:L X GuanFull Text:PDF
GTID:2178360212971605Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
The paper systematically researched the application of FPGA and SOPC technology in the digital communication system on the basis of introduction FPGA and SOPC technology.In this paper, IP core application is researched at first. Designed a high- performance QPSK digital Modulator, Altera NCO2.3.0 offers high-stabilization digital sine signal for QPSK, The experiment result shows, the SFDR and SNR of QPSK modulator is greatly enhanced based on NCO, effectively reduced the hardware cost, the QPSK modulator work stably and reliable. In addition, deeply studies the method to implement high-speed Viterbi decoder based on Viterbi v4.3.0, analyses Atlantic interface, presents experimentation simulation of hybrid and parallel Viterbi decoder. Research result shows, high-speed Viterbi decoder can be designed using Viterbi v4.3.0 to meet different technical requirements.Secondly, the paper studied the FPGA solutions of Digital Multiplex System. Designed FPGA circuit of module including Multiplex, demultiplex, bit synchronization and frame synchronization, mostly performance of bit synchronization and frame synchronization circuit are optimized. The experiment result indicates, bit synchronization circuit can build synchronization quickly, probabilities of miss synchronization and false synchronization of frame synchronization circuit are reduced effectively, design project reduced the hardware cost, the Multiplex System has steady performance.To DSP technology based on FPGA, the thesis proposed a DDS design method base on Dsp Builder, basic DDS module produce 2FSK, 2PSK and 2ASK signal successfully. This DDS's parameters can be adjusted flexibly, simulation result shows, DDS has high resolution and fast settling time.Finally, the thesis researched the software and hardware interface techniques of custom instructions for Nios embedded processor, implemented a 1024 dot plural FFT arithmetic based on IP core FFT V2.2.0 of Altera corporation, proposed a method of custom FFT instructions for Nios.
Keywords/Search Tags:FPGA, SOPC, QPSK, Viterbi decoder, Digital Multiplex System, DDS, Nios
PDF Full Text Request
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