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Research And Implementation Of IPv4/IPv6 Translation Gateway Based On SOPC Technology

Posted on:2007-08-28Degree:MasterType:Thesis
Country:ChinaCandidate:W X LiuFull Text:PDF
GTID:2178360212972200Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
Protocol translation technology will be required during the course of gradual deployment of IPv6. In this paper, seven translation techniques are comparatively studied, and then NAT-PT based on SIIT arithmetic is selected as the translation gateway solution which is oriented to some networks and works on the net layer.As a key device of the heterogeneous network interconnection, gateway has to support high forward rate. Combining the advantages of programmable FPGA hardware and parallel running of VHDL program, IPv4/IPv6 translation gateway solution based on SOPC technology is proposed. At last, the system is implemented on one FPGA chip, which is fine characterized by forwarding packets with 100Mbit/s and 1000Mbit/s, good expansibility, low-delay and system on chip. Being the solid base of creating an ASIC, the main work is the following:1. TCP/UDP, IPv4, IPv6, SIIT, NAT, and the Xilinx FPGA family have been studied, and then an overall scheme is proposed for translation gateway.2. This system is firstly rationally partitioned to some function blocks. Then, DNS-ALG, IPv4/IPv6 translation and TCP/UDP checksum calculation are implemented by VHDL programming and scheme design based on ISE. Finally, simulations of this system in Modelsim are done, and the expected result is obtained.3. An improved model of NAT allowing all IP/ICMP packets to be forwarded is suggested. In this model supporting TCP/UDP transparent transmission, the maximum numbers of sessions that can be set up at the same time by using one registered v4 address are 264.4. Based on "CAM+RAM" which take advantage of the relation between v4 address and memory address, bidirectional query of IPv4/IPv6 mapped address can be realized in one clock period.Based on top-down design idea, VHDL programming and scheme design are both used in the whole design course. To save the system's hardware resources, resource sharing and time sharing technologies are adopted. To improve its speed performance, pipeline technology is used. To enhance its robustness, the state machine design is introduced.The simulation and test results show that expected goal has already been achieved and the performance characters such as the area and speed of this design are perfect.
Keywords/Search Tags:SOPC, FPGA, IPv4/IPv6, NAT-PT, SIIT, Translation Gateway
PDF Full Text Request
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