Research Of Non-Equally Divided Channel Receiver Based On FPGA

Software radio (SR) has become a very important technique in wireless communication. Its basic idea is to place the A/D and D/A close up the antenna as possible as and use software to realize all the function of any radio based on an opening and blocking universal hardware platform.The polyphase filtering channel receiver (PPCR) and non-equally divided channel discussed in this paper, are new techniques which are just applied software radio conceptions. Focus on traditional receiver's troubles such as: non-flexible architecture, update system difficultly, weak ability of multi-signal process and too big system dimensions, this technique improve it with multi-signal process theory and get full probability receiving ability. It costs few resources after been realized, could down-convert the signal's frequency and its sample rate. Furthermore, the platform based on FPGA is opening. System function could easily be updated without any hardware change when it is necessary. All those advantages make good application foreground.At first in the paper, software radio's basic theory is discussed which involves sampling theory and multi-rate signal process, and then math module of the polyphase filtering channel receiver is inferred, and based on it, non-equally divided channel theory is analyzed.The following parts which are system emulation and realization, first introduce the flow of modern DSP development facility-DSP Builder, and then expatiate how to use it to develop the primary part: polyphase filtering module and Fast Fourier Transform module of channel receiver. Finally, figures generated by system emulation and realization are analyzed.This paper mainly researches how to realize arithmetic on hardware in lab stage. The production can be used for following research and is worthy for reference in communication systems which are used software radio concept in.