Research On DFT Technique For Embedded SRAM

As the technique of information is developing, the design of IC becomes more and more complex. It raises quit a lot of challenges for the manufacturing of ASIC. And as the number of pins increases, the quality of the chips degrades. How to find out the defects in the manufacturing process as soon as possible becomes an absolutely tough problem. We need an excellent test method to solve it and reduce the time to market. Embedded RAMs have the highest density in the SOC system. They are also the most sensitive device to defects in the manufacturing process. Varieties of embedded RAMs are used in nowadays SOC design. They take majority of the chip area. In order to guarantee the reliability of the data, tests for memories that are fast and efficient are absolutely necessary.In our paper, we concentrate on the topic of DFT (Design For Test) technique for embedded memories. It consists of the following parts:Firstly, we discussed the importance of the DFT technique for SOC system, especially for embedded memories. We also introduce several test methods. After comparing them with each other, we draw the conclusion that MBIST is the most efficient method for memory test.Secondly, we introduced the concept of MBIST for common SRAM in SOC. We also introduce various fault models for SRAM and discuss the mostly used March algorithm. Furthermore, we proposed a FSM (Finite State Machine) based programmable MBIST which can realize several March algorithms.Finally, we proposed a DFT technique called PDWTM (Predischarge Write Test Mode) in order to test the open defects in SRAM cell which are not easy for the conventional March algorithm to test. Unlike previous solutions, which must be conducted at a low speed, the proposed PDWTM can be performed at-speed. Moreover, it can be easily merged with conventional March tests and is able to detect all the open defects in SRAM cells. Furthermore, the proposed solution imposes little extra design effort and negligible hardware and performance penalties. We simulated the test with SRAM SPICE models to validate the effect of the proposed method at the end of the paper.