Study On The VLSI Design Methodologies Of Video Codec

Latest video coding standards, such as MPEG-4, H.264/AVC and AVS, are characterized by high complexity as well as compression efficiency. VLSI attracts more attention by its advantage on cost, power and efficiency. And the VLSI implementation becomes the mainstream of the video codec design. Low cost is of vital importance to video application with a great quantity, so study on the VLSI design methodologies of video codec is very meaningful.The thesis focuses on the efficient design methodologies of video codec. Based on the analysis of latest video coding standards, methodologies of architecture design, memory design and module design are studied intensively. Furthermore, these methodologies are utilized in the implementation of AVS codec, which shows high efficiency.In architecture design, tradeoff among coding efficiency, hardware cost and coding speed in encoder architecture design was analyzed. Pipeline technique was studied to exploit the parallelism of video coding algorithms. Methods of delay concealment and compression storage are studied in memory design to increase bus efficiency and storage efficiency. Hardware reuse, speed-cost joint optimization and pipeline balance design are illustrated in module design.Based on the analysis of AVS coding algorithms, a hybrid-pipeline architecture was proposed for AVS encoder. By utilizing the characteristics of off-chip memory, the frame storage organization of AVS encoder was designed. Data compression storage method was utilized in the storage of AVS Variable-Length-Coding tables and a reduction of 30% was achieved in memory cost. Hardware reuse, speed-cost joint optimization methodologies were utilized in the implementation of intra-prediction, variable length decoder for AVS with 70% reduction in hardware cost and residual reconstruction for AVS encoder with 400% speedup in medium quality.At last, variable length encoder for AVS was implemented utilizing several methodologies. Owing to the well-designed hardware architectures, the encoder achieved considerable optimization with 61.5% memory cost reduction and 60% hardware cost reduction in Exp-Golomb encoder.