The Design And Realization Of On-Chip Debug Structure For YHFT-DSP

DSP (Digital Signal Processor) is a kind of embedded processor for digital signal processing. It is a good idea that introduces the Design-for-Debugging method into the design process of DSPs, which can effectively support the On-Chip debug after manufactured.YHFT-DSP is a series of 32-bit high performance DSP which is designed by the YHFT-DSP Design Group of the Computer School of National University of Defense Technology. In this paper, based on the study of characteristics of the YHFT-DSP structure, combining the Design-for-Debugging method with the On-chip debug technology and the requirements of application, we designed and realized the debug structure based on HPI. We implemented the high efficiency debug communication and control channel through HPI structure. And we designed the basic debug characteristics through the control of the pipeline, such as single step and breakpoint. We also proposed an accessing mechanism of the address space, which is suitable in application platform for YHFT-DSP.We designed and implemented the JTAG boundary scan structure. We combined the boundary scan structure with the debug structure based on HPI, and we realized the debug structure based on JTAG boundary scan. Without adding new hardware interface on PCB, this debug structure can implement On-chip debug through the JTAG interface which is necessary to each PCBs.RTL-level coding for both debug structures of YHFT-DSP was finished, and complete simulation vectors for the design were developed to ensure the correctness of the design. Both of the debug configurations have been put into practice in YHFT-D3B and YHFT-D4B high performance DSP.During the verification after YHFT-DSP manufactured, both debug structures can be supported by YHFT-DSP IDE. Actual result of On-board debug shows that both of the debug structures can work well. In addition, we designed JTAG emulator to support the debug structure based on JTAG boundary scan.