The Research And Hardware Implementation Of Wavelet Transform And EBCOT Based On JPEG2000

With the development of Internet and multimedia technology, the information becomes more and more, and the limited storage and bandwidth is become the bottleneck. So it is necessary for the effective processing and compression of information. The latest still image compression standard JPEG2000 adopts Discrete Wavelet Transform and Embedded Block Coding with Optimized Truncation (EBCOT), and achieves much better coding efficiency and image quality than the traditional methods. With its excellent performance and prominent features, JPEG2000 will no doubt become the main-stream in the image compression field in the future. But it is hard for hardware implementation of JPEG2000. High attention is paid to design VLSI architecture for DWT and EBCOT implementation with real-time, low area and energy dissipation.Firstly, this thesis analyzes the process of JPEG2000 encoder. Then this dissertation deeply accessed the hardware implementation techniques for DWT, bit plane coding and binary arithmetic codec used in JPEG2000.As for the VLSI implementation of discrete wavelet transform (DWT), the row based method and parallel architecture is adopted for the 2-D DWT, which makes both the transform speed and the efficiency increase. With combining the data-extension procedure into the DWT core, the memory requirement and memory access of DWT can be reduced. And the architecture can accomplice multi-level DWT for the whole image using only 6 rows of inner single-port RAM. As for the hardware implementation of bit plane coding, a bit plane coder based on coding-pass parallel processing is presented. The three scan procedures of the algorithm for bit plane coding in JPEG2000 is incorporated into one scan procedure. The accelerator is efficient, and area is not large. As for the VLSI implementation of binary arithmetic codec, the binary arithmetic codec based on three-pipeline architecture is presented, which improves the encoding efficiency with encoding one data every clock. At last, the three proposed architecture is implemented in Verilog HDL. The result of simulation and synthesis of the proposed architecture proves the design.