The MPEG-4 Codec Design Base On SoC

Along with the fast IC technology development, MPEG-4 is widely used into portable device. To meet this market demand, some hardware codec chips or solutions appeared in the market. Since they are designed base on ASIC technology, they have shortage in flexibility and platform portability. SoC technology is developed in the late 1990s of last century. It has the advantage over ASIC in much aspect. Researching how to use software to realize SoC MPEG-4 codec not only has technical value, but also market value.The main content of this paper is from the perspective of a software designer,discussed the structure of such a MPEG-4 codec chip and its software design method. Since this chip is designed for mobile phone to expand their multimedia function, much special requirement is carried out to fit for the platform, such as low power, small size and compatibility. This design is base on SoC technology. Software is the main codec, and hardware for accelerate. By carefully analyze and configure, this design successfully reach the aim by lower software and hardware cost. Compared with other product which and be seen in this field, this design has some advantage at develop speed and flexibility.In this design, software take the main role of encode and decode. So, software designer should act as an architect, join the whole developing flow to offer their requirement and design from hardware to software. In hardware architecture design, we analyze the whole decode and encode flow, figure out the key data path, list main feature and demand. After that, we take 3DSP SP3R5m as the system's core. We also analyzed the DSP's feature, to enforce its power, many hardware components were selected and designed to improve the system's performance, decrease its power consuming.When developing the software, we use XviD's code as reference and rebuild the whole architecture and optimize the encode and decode flow. To take full advantage of the hardware device and co-processor, a new structure is developed to enable the hardware and software work together. To speed up the decoding and encoding, we scan the key work path and use double block DCT, optimized VLC and simplified ME analysis to optimize the key node. The memory size is also estimated, and by reusing and cutting off, the memory size is also minimized.Verification of software and RTL shows that this design can fully realize the design spec.