The Design Of A SRAM Based FPGA Device

Field-Programmable Gate Arrays (FPGAs) are integrated circuits which can be programmed to implement any digital circuit. To implement digital systems with FPGA have the advantage of flexible, low-cost, low-risk, low-turn-around time and so on. At the background of the previous work of FPGA devices internationally, This study is began on the structure of the FPGA and it focued on optimizing the interconnect resources of FPGA. Be compared with the ASIC, much of the area and speed penalty to the FPGA is due to the programmable routing structures. This happens because in FPGA, gates are connected with programmable switches and metal wires, but full-fabrication chips use simple wires to make interconnections between logic gates. These switches have much larger resistance and capacitance and hence are slower than the wires in full-fabrication chips. This indicates that we can improve the performance by optimizing the programmable interconnect method and the interconnect structures. In this thesis, The effect of the logic modules and interconnect resources on the SRAM based FPGA devices is studied, First the basic system architecture was introduced in this paper, and following we studied the switch matrix and got a more flexible switch matrix architecture which combined the character of the Wilton switch matrix and the Disjoint switch matrix, the new switch matrix help to improve the routable rate notably. Then the length of the general programmable wire, the programming connect techniques and the width of the routing channels were also researched and the general routing architecture that suite for the moderate or small scale FPGAs was got, the simulation showed that the new routing architecture had a good performance on speed and area and got a better trade-off between them.Then the programmable logic resources was studied and a moderate scale coarse-grain logic cluster, this logic cluster has a Xilinx products semiarid structure of LUT and Flip-Flops combination, this structure makes the Basic Logic Cells'connection in the Logic Cluster more closely and improves the Logic Cluster's function. Then the number of the IO modules and the programming circuit to the distribution-style SRAM resources were studied, and the transistor level design of the SRAM cell was also introduced. Finally, a FPGA device was designed on the basis of our study work and the test scheme was also designed, As a key project of CETC58 institute, now this chip has been fabricated under the CSMC 0.6μm 2P2M process. The test results show that it achieves the anticipated performance.