Research And Implementation On SCI-node Based On FPGA

The national 863 project"Development of FC board for the Flight-controling computer system"is to design an FC board compliant with CPCI bus standard. This subject is the further extension of the project, which is to design Scalable Coherent Interface (SCI) for high-speed serial communication among multiprocessor systerms.Under this background, the SCI-node is researched and designed in this thesis. At first, introduce the SCI protocol and SCI-node model in general. SCI is an interface standard for very high performance multiprocessor systems. It supports a coherent shared-memory model. SCI's low pin counts and simple ring topology make it cost-effective for small systems as well as for the massively parallel ones. A SCI-node includes a sending RAM, a receiving RAM, a bypass FIFO, an address decoding module, a multiplexer (MUX) and high-speed serial interface. Then introduce how to implement the SCI-node in detail in embedded development kits (EDK). It is with the block RAM to design the sending RAM and the receiving RAM. Design a synchronous FIFO to implement the bypass FIFO. It is with the RocketIO to implement the high-speed communication and with Aurora IP core to implement the Aurora link layer protocol. The address decoder and MUX are implemented in the control logic. It is with the OPB-PCI bridge to implement the CPCI .It is with the SOPC solution to implement the FPGA logic. The FIFO is designed in Verilog, and the Aurora module is designed in VHDL. The function and timing simulation by ModelSim is done in Xilinx ISE. Then the whole design is implemented in EDK. At last the design is downloaded into the PROM in the development board, and is verified by ChiopScope Pro.The SCI-communication is tested between computer A with a FC card and computer B with a FC card under Windows OS 2000. The result shows that the direct transfer-speed between A->B is 3.4MB/s now, and the transfer-speed among A->B->A with bypass FIFO is 0.88MB/s now.The reason of the low transfer-speed is discussed at the end of this thesis. It also points out the problems and the further work.