Design A 2W HVMOS RF Power Amplifier

Due to the intensely market competition, wireless communication systems demand low cost, low power and multi-function for RFIC. In this condition, comparing with so many processes, the CMOS process can fulfill those demands only. On the other hand, owing to the characteristics of CMOS technology, the bottleneck of RFIC design is power amplifier design.In this paper, the detail steps of power amplifier design are presented. We design the power amplifier according to the industrial design specification. The limitation of power amplifier design in CMOS process is analyzed first. Then we construct and analyze the model of power transistor by using Matlab software. The CMOS power amplifier design methodology and fixed method are then presented. In this paper, a 2W class AB CMOS RF PA in JAZZ 0.5um process is designed. The operation frequency of the PA is 1.8GHz. The input match, output match and bias circuit are implemented with discrete off-chip elements. The specifications are referenced to NE5510279A, the PA can be applied in GSM handset, the effect of real bond-wire parasitical inductor when packaging is considered in the schematic design. The detailed design flow and the layout of the power transistor are proposed also. Simulation results show that when the PA operates at 1.8GHz and the input power is 25dBm, it has a 32.67dBm output power, 40% PAE and 800mA operation current, and the input 1dB compression point is 24.6dBm.