Design Of Two CMOS Serial Communication Interface Chips

With the great development of information technology, the interconnection and data transmission between computers have become more frequent. Multiple communication protocols have emerged. The importance of a standardized interface chip for a well performanced electronic system has become more apparent. In-depth research on two kinds of interface chip is conducted in this paper.First, the article gives two popular communication protocols: RS-422 and LVDS. The advantages and disadvantages of both are analysed. The former electrical characteristic is defined by TIA/EIA RS-422B, which employs differential transmission to improve the communication reliability and distance. RS-422 has strong common mode interference rejecting ability. But the data transmission rate is relatively low. The latter's full name is Low Voltage Differential Signal, which has many distinguish features such as high-speed, low-power, low bit error rate, low crosstalk, low radiation, and so on. So, LVDS is more widely used in systems that require high signal integrity, low jitter and strict common mode characteristic.Second, two standardized interface ICs, respectively meet TIA/EIA RS-422B and ANSI/TIA/EIA-644 standard are developed. The RS-422 interface chip is a four-channel differential output line driver, which can transfer a CMOS/TTL signal to a pair of differential signal. The differential output voltage is 2.73V, and the date rate can reaches up to 10Mbps.Power-on reset and TTL compatible interface is featured. LVDS interface chip is a single-channel differential output line driver. The transmission rate of LVDS driver is up to 500Mbps, output current is 3.4mA, and differential output voltage is 300mV. The built-in precise bandgap reference and common-mode feedback circuit can restrict common mode output level steady at 1.24V.Thirdly, after the completion of circuit design, CSMC 6S05 DPTM -ST2100 design rule is utilized to fulfill the layout. Device match is emphasized in layout design, which minimizes errors caused by mismatch; ESD protection circuit is added to enhance the antistatic capacity of whole chip; The guard ring and floorplan is carefully designed so that the latch-up can be avoid. Through DRC/LVS verifying, the final GDSII format date is generated and delivered to manufacturers to taped-out. Now, the sample of RS-422 interface chip has been received. It behaves well under test.