Design And Implementation Of Multi Link Hd Image Data Stream Acquisition Circuit

In recent years,with the rapid development of image acquisition technology,the collection of massive high-definition image data has increased exponentially,and it has gradually become a trend to transmit the collected massive high-definition data to the computer through the acquisition equipment.This results in low real-time performance,low speed and low accuracy of data transmission.On this basis,it is very important how to transmit massive high-definition data to the host in real time and quickly for later data processing.Therefore,this paper designs and implements a high-speed data acquisition board circuit with FPGA as the core,utilizes the collaborative and efficient processing between FPGA internal modules,and realizes the interconnection between the host and the acquisition device through the PCIe interface,and finally realizes the real-time 4-channel high-definition LVDS data.,high-speed and accurate transmission.The main work of this paper is as follows:1.Design and implement the high-speed data acquisition board circuit with FPGA as the core.Taking ALINX AC7A200 as the control core,select and design the schematic diagram of each chip in the board,including serial LVDS interface circuit,power supply circuit,PCIe interface circuit,FPGA expansion circuit and LAN circuit,USB to serial port circuit design,and according to The resistance,current and voltage values in the voltage calculation circuit are designed,the high-speed data cache management structure is designed,and the PCB layout is completed.2.Implement the overall logic design within the FPGA.Including input FPGA internal4-channel LVDS signal logic processing,massive high-definition data cache logic principle and PCIe interface logic design.First,analyze the logic of the bus AXI,compare the advantages and disadvantages of DMA bus transmission and PIO transmission based on the AXI protocol interface,and complete the data calling logic of FIFO,AXI bus and PCIe bus.Then the DDR3 memory storage structure is implemented,and the high-speed data cache management structure is applied to the DDR3 controller.Finally,the PCIe interface logic is completed,and the logic configuration is performed according to the PCIe IP.The interface logic design includes the DMA logic design and the user logic design,and the continuity of data transmission is realized through the interrupt logic design.3.Design and develop host computer software.Modular design of the host computer software,including the Windows platform PCIe bus driver,control program and software interface layout,combined with XDMA,FIFO and bus PCIe logic,to achieve the host computer software data read and write functions and display,and finally tested.And verification.The experimental results show that the FPGA data acquisition card can receive and process the data transmitted by four channels,and the fusion data of 1024*1025 and640*513 pixels does not lose frames during the transmission process.Under the AXI clock frequency of 125 MHz,the read and write of the PCIe interface The speed can reach510.36MB/s and 770.66MB/S respectively,which meets the design requirements of highspeed transmission of the system.