The Design And Implementation Of RS-485 Transceiver

Based on the RS-485 communication protocol, this paper designes an RS-485 Tranceiver, using ASMC 1.2μm BiCMOS technology and Cadence Spectre simulation tool. It is two-way, half-duplex communication, and the normal operating temperature range is -40℃to 90℃. It has 230μA low quiescent current,±15kV Electro Static Discharoe protection, 12ns propagation delay and the three-state output etc. It can be used in data collection and control systems.In this paper, the RS-485 Tranceiver is in manner of balanced driving and differential receiving, that is, in the transmitter, the driver tranforms TTL into differential signal; and in the receiver, it tranforms differential signal into TTL, it eliminates the influence of ground shifts and induction noise signal appeared as common-mode voltage in the network, and it has the capability of strong suppressing common-mode interference. The chip is composed of transmitting and receiving modules. The transmitting module achieves balanced driving through the symmetrical digital circuits. It has the structure of typical CMOS three-state output, and the function of short-circuit protection and thermal shutdown; the receiver module is composed of a comparator with hysteresis and a three-state circuit, and choosing -50 mV and -200 mV threshold point makes the chip have open and short-circuit protection, and it has high sensitivity which can detect the voltage as low as 200mV. The driver output is of MOS with large W/L, the PN junction composed of drain and substrate of these MOS is equivalent to a diode with large area, which plays a role of ESD protection, and in the layout design, there are some special protection rings to enhance ESD protection on the pin A and B, which can reach±15kV ESD protection. In addition, the driver slew rate of the chip is not limited, allowing to transimit up to 5 Mbps. Through the simulation, it accords with the RS-485 protocol and achieves the predetermined specifications.The layout design is based on the Design Rules, and the most crucial part is the layout and structure of the output driver circuit, which adopts the resistor shunting to prevent local overheating and isolates the large-size digital output PMOS and NMOS to prevent latch-up. It uses Cadence Dracula layout verification tool to achieve the DRC and LVS, and the final chip area is about 2.2 mm~2, and it has been taped out successfully. In contrast with other similar products, it has the advantage of low cost, small size, low power consumption etc.