Design And DSP Implementation Of Digital Receiver Demodulator

Digital receiver of satellite is the trend of future electronic system development. Demodulator is a key part in a receiver and the difference between an analog receiver and a digital receiver begins from it. The design of digital demodulator plays an important role in digital receiver development. Now, fast development of digitalization theory and microelectronic technology provides necessary support for the design of digital demodulator.The paper is composed of design of carrier synchronization loop and design of bit synchronization loop. Carrier synchronization loop is based on the structure of Costas loop, which is widely used in many projects. The design of loop is based on the selection of parameter. A set of scheme for the parameter selection and verification is proposed.The interpolator loop which proposed by Gardner is used as bit synchronization loop in this paper. This loop has never been used in the past projects of our institute. The interpolator loop does not need to synchronize sampling clock of A/D converter with bit clock. It directly re-samples digital signal through sampling rate conversion technology. A simple timing error detection algorithm assures the re-sampling points are the best symbol decision ones. The operation function of interpolator loop assures bit synchronization loop to be independent from carrier synchronization loop, simplifies the system structure, and provide ideal phase synchronization effect. Especially, this loop is very suitable for the bit synchronization in digital signal processing method.A solution for the construction of a digital demodulator is proposed in the paper. After scheme verification by MATLAB, available FPGA and DSP components are selected to realize it's hardware.