Physical Design And Verification Of SOC Based On 51 Core

The IC layout is a necessary step in the IC manufacturing process.It not only decides function of IC,but also affects performance,cost and power of IC at a large degree.In deep submicron technology,as the ratio of interconnect delay rises dramatically in whole chip delay,the timing closure become the most important issue of layout.The main task of IC layout is P&R(Placement and Routing).The major research of the paper is the P&R flow in deep submicron process based on Astro,the physical verification process based on Hercules and the STA based on Prime Time.Firstly,the physical design tool——Astro and the STA tool——PT are introduced.Secondly,we sum up the main delay models,parameter extraction and timing optimization.Thirdly, we build the backend design flow of GVC chip which is a SOC chip based on Charter 0.35um process using Astro.The emphasis of this thesis is the four key steps of GVC backend design:Floorplan which implements the placement of Macro Cell manually and power/ground routing based on IR Drop and Electromigration;Placement that implements standard cell placement in timing and congestion driven mode,which consider the performance and routability;CTS and routing,in this step we use the method of CTS considering gated clock and distributed routing which brings dramatic reduction of in overall routing time.We address the principle,steps and scripts related to the four steps.In the fifth chapter,we introduce the process,principles and results of physical verification.We introduce the STA and verify that the timing of the chip is closure.Finally,the summary and outlook of the whole research are given.