Physical Design Of Great Template Convolution Embedded PLL ASIC

The back-end design of integrated circuits is an important part of connecting the chip design and chip manufacturing, which means translating the front-end code that has been verified to the physical layout file which can be used in manufacturing. It is a complete process which covered logic synthesis, place and route, timing analysis and physical verification that based on a certain kind of process design kit. Then we can get the layout file with best result of power and timing optimization that can be tape out.In this paper, it describes the physical design process ofgreat template convolution embedded PLL(Phase-locked loop), which focused on solvingembedding PLL and the floorplan, timingoptimization, placement, routing, and physical verification of mixed-chip with PLL. The total design process is as follow: first, we need to establish a physical model of the PLL that placement and routing tool calls; secondly, PLL interconnections is defined in the topmodule, analyze of interface timing information and complete the physical synthesis; then, we should acomplish the floorplan of mixed layout, power network synthesis, CTS; finally, to generate a layout file for physical verification.On timing optimization, considering issues of embedding PLL, we should analyze the timing of PLL embedded path based on interconnection information. Since there is no detailed internal timing library file of the PLL(analog IP), so, when we set timing constraints, we should consider the overall startup time of PLL in order to ensure the Chip timing constraints reasonable.On building the physical model of PLL, firstly modify the layout filebased on the original chip layout physical informationand the mixed-design requirements. Then the physical layout of the lef file is extracted. Finally the FRAM of a physical model is created basing on the layout file and LEF information in the order toachievethe floorplan andembedded PLL.In the floorplan, It is different to the traditional digital back-end layout process. First, according to routing of the mixed interface and the PLL(analog IP) physical information, we need determine the placement of embedded PLL, and make sure that the analog and digtallayout which is adjacent to the position is isolated to prevent noise transmission and achieve the electrostatic protection. Finally we should finalize the digital part of the floorplan in accordance with conventional methods, ensure that the digital part of the voltage is Stable.Finally, after placenment and routing, we can get a low-power and timing optimal layout file, the file physical verification is verified and emulated to ensure compliance within production design rules.Then do functional simulation after complete verification of layout data. According to the result, we can find that maximum operating frequency of chip is 125 MHz, the power is 657 mw, the area is 3.742 mm * 3.746 mm, the number of pins is 97. Can be do convolution operation in real-time for512 * 512 * 8bit @ 110 frames with 40 * 32 * 8bit template, the output bit width is 27 bit, chip data rate of 230 Mb / s, the result achieve the intended technical indicators. At present, the design has already been submitted.