Font Size: a A A

Design Of Image Compression Card Based On SPIHT Algorithm

Posted on:2008-05-19Degree:MasterType:Thesis
Country:ChinaCandidate:J WangFull Text:PDF
GTID:2178360245498005Subject:Instrument Science and Technology
Abstract/Summary:PDF Full Text Request
Digital images are widely used in many fields such as national defense, industry and social life. As the tremendous image data is a great challenge to transmission and storage, the real-time hardware image compression becomes necessary. This thesis focuses on the design of the image compression card based on Set Partitioning in Hierarchical Trees(SPIHT) algorithm.This thesis first introduces the possibility and the methods of image compression in general. The discrete wavelet transform(DWT) combined with SPIHT coding is adopted as the approach to compression in consideration of efficiency, hardware expense and design complexity. In the theory part, lifting scheme, integer 5/3 wavelet transform and wavelet based image compression are introduced, followed by the description of original SPIHT and its modified non-list algorithm. In hardware design, the overall scheme is determined according to the requirement of image compression card. The circuits of video image sampling unit based on chip SAA7111A, data buffer unit, image compression and control unit based on FPGA and USB interface unit are described in detail. In programmable logic design, the modular structure of image compression is illustrated in the beginning, and then the ideas and implementations to 4-level integer 5/3 wavelet transform and modified SPIHT coding in FPGA are expounded. The logic is described in Verilog HDL which enhances its generality and portability. Pipelining and partitioning are taken into the compression logic design so that the process ability of the system is improved, meanwhile the memories and the cost are reduced greatly.The approach to image compression is approved by MATLAB simulation. Compared with the MATLAB result, the wavelet transform and SPIHT coding logic is analyzed after timing simulation in Quartus II. Then process speed and memory amount is evaluated. At last, the compression card is debugged in video condition. The result confirms the logic runs as expected and the card is capable of processing images with 512×512 pixels in rate 25f/s, achieving relatively high compression ratio with image quality loss in a limited range.
Keywords/Search Tags:image compression, discrete walevelet transform, non-list SPIHT, FPGA
PDF Full Text Request
Related items