Research Of DMA Module Design In 32-bits Floating-point DSP Processor

DSP processor plays a very important part in the high performance modern communication and information processing SOC systems. And the series of TMS320C3X, 32 bits floating-point DSProcessor, have a lot of advantages, such as high operation speed, large numbers of data throughput and good real-time processing performance. This paper mainly introduces the design of DMA module IP soft core based on improved VC33 processing core.The DMA module is an important part in DSP systems. The application range of DSP systems is restricted, because of the disadvantages of original DMA module, such as simplex function, unskillful addressing mode and small addressing range etc. According to the actual using conditions of the DSP system, some functions such as index addressing, bit reverse addressing, floating-point format transform between TI and IEEE, auto initialization are added in DMA. It expands the application range of the DMA system. In addition, a data pipeline channel with two levels is also added in the DMA structure, realizing the non-synchronization single-cycle transfer between RAM and peripheral devices without increasing the number of data register, greatly speeding up the data transfer speed in this condition. At the same time, some characteristics are reserved in the DMA, such as the non-synchronization double-cycle transmission between RAM and peripheral devices and the synchronization transmission using interrupts.Referring to the DMA function and theory described above, this paper analyzes functions and behaviors of the primary DMA module at first, and then designs the new system structure referring to the new added function modules and the original structure, resolving the problem of assembling them in the new system structure. At the same time, this paper describes the meanings of designing new functions, and then formulates these functions and time model of the new structure, expatiates the relationship of the module's internal control channels, addressing channels and data channels,basing on this, introduces some details of the each sub module in the DMA structure according to decoding part, control part, addressing and data transfer part.By using TOP-DOWN design strategy of digital system, I partition the DMA module in RTL, and describe the function using Verilog HDL, realizing the design of control FSM, decoding circuit, address generating module, interrupt generating logic and auto initial FSM etc, and optimize the Verilog code. And then, I write lots of simulation test code by modifying every control bit in control register, and finish the all-around test and timing analysis of the DMA module's each function totally. The results of simulation make it clear that the design achieve the requirement of system design. Finally, this paper analyzes the problems such as the DMA performance and compatibility in application etc.