Implementation Of A Configurable Viterbi Decoder With FPGA

As a class of important forward error correcting codes, the convolutional code is adopted extensively in various communication techniques and standards (e.g., WiMAX, LTE and UMB), in conjunction with the maximum-likelihood performance-achieved Viterbi decoding algorithm. In particularly, the parameters of convolutional codes are usually different in various standards. Note that the conventional fixed Viterbi decoding core is only designed for some fixed parameters and suitable for a certain communication standard. Therefore, it is important and interesting to design a flexible Viterbi decoding core which is compatible with various standards, especially for supporting integrated services.In this thesis, with the application of the convolutional code in wireless access standards (e.g., WiMAX, LTE and UMB) and the full consideration of trade-off between resource utilization and data rate, the design of a Viterbi core is investigated based on the analysis of the Viterbi algorithm, which supports the three wireless access standards and dynamic parameterization. The configurable parameters include standard type, trace-back length and the initial state for trace-back. These parameters enter the decoder, together with the corresponding received data, and then the decoding can be performed reliably under the condition of dynamic configuration. The novel data control mechanism is introduced in the decoder architecture for the purpose of the reliable decoding for massive data flow. The pipeline architecture, which is properly used in the whole decoder, improves high data rate obviously. It is verified that the correct and reliable decoding, along with the configurability works well. Data rate of 100Mbps for WiMAX and 4Mbps for LTE or UMB can be achieved. Resource utilization is equivalent to that of Altera core with the same parameters.