Design Of Codec For Quasi-cyclic LDPC Codes And Its FPGA Implementation

Quasi-cyclic (QC) low-density parity-check (LDPC) codes form an important subclass of LDPC codes. These codes have encoding and decoding advantages over other types of LDPC codes.For example, a class of new codes with different code rates can be got by adjusting the corresponding parameters easily, and they can be encoded by shift registers which lowers the encoding complexities, and the decoders also have low complexities.Currently, QC-LDPC codes have been one of the schemes in the CCSDS deep space communication standard.In this dissertation, some key problems of the codec for QC-LDPC codes are investigated by theoretical analysis and simulation. The main works are summarized as follows:The Sum-Product algorithm, Min-Sum algorithm(MSA) and Normallized Min-Sum algorithm(MMSA) decoding theories of LDPC codes are systematically summarized. The encoding algorithms for LDPC codes especially for QC-LDPC codes are also introduced.Based on principles of Modified Min-Sum algorithm, the FPGA implementation method of decoding for QC-LDPC codes are proposed, and all the modules in the FPGA design and the hardware simulation results are also introduced.The serially concatenated systems under different encoding algorithms are performaced. Moreover, the modules adapted to be implemented using FPGA hardware are proposed as well as the simulation results.According to the hardware test performances, the codec design satisfies the index requirements of CCSDS standard and it can be used in the deep space communications.