Implementation Of Key Techniques In AVS Intra-decoding Based On FPGA

In the past decades,the rapid development of global information technology has driven the rapid popularization of digital video.At the same time,a higher compression efficiency algorithm is in good need.AVS is a video coding standard,which is developed by China herself.The high compression efficiency and simple implementation architecture to others make its foregroud widely.A lot of company and research institute begin to study and make use of such new standard.Because the decoding complexity of AVS is very high,software implement cant't decode in real-time.The decoder must be implemented in hardware.Implementation of key techniques in AVS intra-decoding based on FPGA,which includes entropy decoding,anti-scaning,anti-quantifing andⅡCT,are given in this dissertation.We define the interface between the code-division unit and entropy decoder unit at the beginning,then a careful demonstration for the design of entropy decoder is given.Parallel structured variable length decoder which is adapted in the design bases on barrel shifter.It is the essential architecture to achieve real-time decoding because it can get a much faster speed in the decoding than that of serial structured decoder.However,even with barrel shifter,the traditional entropy decoder architecture is hard to achieve real-time decoding based on the popular FPGA.After the analysis of the traditional entropy decoder architecture,an new structure with a 43.2 percent timing improvedment is given at the cost of the lose of 2.5 percent LE,which plays a important role in the spreading of this design.After that,we proposed a data organizing format to connect the data-stream between the entropy decoder unit and the anti-operation unit.The special data organizing format not only saving storage,but also provising a concise programme in anti-scaning with speed,synchronizing for scan-mode and quantifid QP.At last,some advanced techologies are adopted and the relative improvement are made in anti-operations to saving the storage under the condition of real-time decoding.We use a top-down method to direct the design.And the C code has been used to generate the test vectors for verifying the verilog modules.During the design with Verilog,we go simulation module by module.In this way,we can detect and solve the errors in time so as to guarantee the design is what we want too.The whole design has been verified by FPGA.The experimental result shows that the architecture proposed in this dissertation can decode the high-definition video(4:2:2) in real-time for AVS on CycloneⅡEP2C35F672C6.