Gate Leakage And Soft Breakdown Properties Of Small-Scaled MOS Device

The CMOS technology has become the prevailing technology for the VLSI application today. In the past 20 years, the feature dimension of MOSFET is always following the Moore's law and significantly scaled down. As a result, some device structural parameters approach to their physical limits gradually. Many challenges in fabrication, physics, and design appeared.In the paper, the developments of IC technology are introduced firstly. Then a brief analysis about the device structure, processing, physical and quantum effects are given out. Secondly, we calculate the quantum effects of the carriers in the inversion and the direct tunneling current through the gate oxide. In the end, the post soft breakdown current is discussed.In order to calculate the electron tunneling current through ultra-thin-oxide NMOS more preciously, quantized energy levels and electron density distribution are calculated by solving the one-dimensional Schr?dinger equations and one-dimensional Poisson equation self-consistently. Because the WKB approximation, the conventional method used to calculate the transmission coefficient is inaccurate in regions where the potential profile varies abruptly, we choose the multi-step potential approximation for the oxide potential barrier to calculate quantum mechanical transmission probability. The direct tunneling current with decreasing the thickness of gate oxides layer were analyzed under various gate voltage. Considering the depletion effect in poly-silicon and the multiple energy valleys in Si substrate, the tunneling current increases exponentially as the oxide thickness is scaled down. Comparison of simulation results with experiment data verifies the validity and extensive applicability of this model.Considering the change of periodic lattice after soft breakdown (SBD), the impact of soft breakdown to dielectric coefficient and carrier effective mass is advanced. A new method to calculate the post soft breakdown current is presented. By selecting the dielectric coefficient and carrier effective mass properly, the current-voltage characteristics of ultra-thin oxide after soft breakdown can be calculated in an easy and effective way. A new type processing of high-k dielectric gate MOS device is studied. The effects of post deposition annealing in NO ambient on the electrical properties of MOS device are studied. Capacitance-voltage, gate-leakage and soft breakdown properties are characterized and compared. It is found that NO annealing sample exhibits good electrical properties: lowest interface-state density, lowest gate leakage current and highest reliability due to form an interlayer of HfTiSiON like SiO₂/Si interface.